The present invention relates to a common bus control method in an electronic switching system.
A conventional electronic switching system includes a plurality of units of, e.g., unit numbers 1, 2, and 3 shown in FIG. 6. The plurality of units are connected to common buses 210, 211, 212, 213, 214, and 215 through transceivers 200, 201, 202, 203, and 204. Data transmission/reception interface sections 13, 23, and 33 of the respective units establish frame synchronization of time-divisional slots of the common buses by using a frame head signal generated by a synchronization frame head signal generator 90 of the first unit. In addition, the interface sections 13, 23, and 33 latch and transmit data of the common buses in response to signals transmitted from a system fundamental clock source 91 of the first unit. Referring to FIG. 6, reference numerals 80, 81, 84, and 85 denote drivers; and 82, 83, 86, and 87, receivers.
In the above-described electronic switching system, the respective units perform data transmission/reception through the common buses in accordance with two signals output from the synchronization frame head signal generator 90 and the system fundamental clock source 91 of the unit having the unit number 1. For this reason, as shown in FIG. 7, an absolute difference in timing between the two signals is made due to delay between the drivers 80 and 81, and the receivers 82 and 83, and cable delay between the units. Since the respective units have different absolute timings of data transmission/reception with respect to the common buses, data A transmitted from the data transmission/reception interface section 33 onto the common bus 211 may not be properly received by the interface section 13 of the unit number 1, although the data A can be properly received by the interface section 23 of the unit number 2.
That is, in the conventional method, since data of the common buses are transmitted/received in accordance with a fundamental clock and a synchronization frame head signal transmitted from the fundamental unit, the number of units is increased, and data transmission/reception is adversely affected by delay of each unit. As the unit number is increased (delay from the fundamental unit is increased), the margin between data and its latch signal is reduced. As a result, the number of units is undesirably limited.